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functional block diagram rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a 12-bit ultrahigh speed multiplying d/a converter AD668 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features ultrahigh speed: current settling to 1 lsb in 90 ns for a full-scale change in digital input. voltage settling to 1 lsb in 120 ns for a full-scale change in analog input 15 mhz reference bandwidth monotonicity guaranteed over temperature 10.24 ma current output or 1.024 v voltage output integral and differential linearity guaranteed over temperature 0.3" skinny dip packaging mil-std-883 compliant versions available product description the AD668 is an ultrahigh speed, 12-bit, multiplying digital-to- analog converter, providing outstanding accuracy and speed per- formance in responding to both analog and digital inputs. the AD668 provides a level of performance and functionality in a monolithic device that exceeds that of many contemporary hy- brid devices. the part is fabricated using analog devices complementary bipolar (cb) process, which features vertical npn and pnp devices on the same chip without the use of dielectric isolation. the AD668s design capitalizes on this pro- prietary process in combination with standard low impedance circuit techniques to provide its unique combination of speed and accuracy in a monolithic part. the wideband reference input is buffered by a high gain, closed loop reference amplifier. the reference input is essentially a 1 v, high impedance input, but trimmed resistive dividers are pro- vided to readily accommodate 5 v and 1.25 v references. the reference amplifier features an effective small signal bandwidth of 15 mhz and an effective slew rate of 3% of full scale/ns. multiple matched current sources and thin film ladder tech- niques are combined to produce bit weighting. the output range can nominally be taken as a 10.24 ma current output or a 1.024 v voltage output. varying the analog input can provide modulation of the dac full scale from 10% to 120% of its nominal value. bipolar outputs can be realized through pin-strapping to provide two-quadrant operation without additional external circuitry. laser wafer trimming insures full 12-bit linearity and excellent gain accuracy. all grades of the AD668 are guaranteed mono- tonic over their full operating temperature range. furthermore, the output resistance of the dac is trimmed to 100 w 1.0%. the AD668 is available in four performance grades. the AD668jq and kq are specified for operation from 0 c to +70 c, the AD668aq is specified for operation from C40 c to +85 c, and the AD668sq specified for operation from C55 c to +125 c. all grades are available in a 24-pin cerdip (0.3" package. product highlights 1. the fast settling time of the AD668 provides suitable perfor- mance for waveform generation, graphics display, and high speed a/d conversion applications. 2. the high bandwidth reference channel allows high frequency modulation between analog and digital inputs. 3. the AD668s design is configured to allow wide variation of the analog input, from 10% to 120% of its nominal value. 4. the AD668s combination of high performance and tremen- dous flexibility makes it an ideal building block for a variety of high speed, high accuracy instrumentation applications. 5. the digital inputs are readily compatible with both ttl and 5 v cmos logic families. 6. skinny dip (0.3") packaging minimizes board space require- ments and eases layout considerations. 7. the AD668 is available in versions compliant with mil- std-883. refer to the analog devices military products databook or current AD668/883b data sheet for detailed specifications.
AD668Cspecifications (@ t a = +25 8 c, v cc = +15 v, v ee = C15 v, unless otherwise noted) C2C rev. a AD668j/a AD668k AD668s parameter min typ max min typ max min typ max units resolution 12 12 12 bits lsb weight (at nominal fsr) current 2.5 * * m a voltage (current into r l ) 250 * * m v accuracy 1 linearity C1/2 +1/2 C1/4 +1/4 * * lsb t min to t max C3/4 +3/4 C1/2 +1/2 * * lsb differential nonlinearity C1 +1 C1/2 +1/2 * * lsb t min to t max C1 +1 C1/2 +1/2 * * lsb monotonicity guaranteed over rated specification temperature range unipolar offset (digital) C0.2 +0.2 * * * * % of fsr bipolar offset C1.0 +1.0 C0.6 +0.6 * * % of fsr bipolar zero C0.5 +0.5 C0.2 +0.2 * * % of fsr analog offset C1.0 +1.0 C0.7 +0.7 * * % of v nom / c gain error C1.0 +1.0 * * * * % of fsr temperature coefficients 2 unipolar offset C8 +8 C5 +5 * * ppm of fsr/ c bipolar offset C25 +25 C15 +15 * * ppm of fsr/ c bipolar zero C20 +20 C15 +15 * * ppm of fsr/ c analog offset C20 +20 C10 +10 C20 +20 ppm of v nom / c gain drift C30 +30 C15 +15 C40 +40 ppm of fsr/ c gain drift (i out ) 150 150 150 ppm of fsr/ c reference input input resistance 5.0 v range 5 * * k w 1.25 v range 5 * * k w 1.0 v range 1 * * m w reference range (t min to t max ) 10 100 120 * * * * * * % of v nom data inputs logic levels (t min to t max ) v ih 2.0 7.0 * * * * v v ll 0.0 0.8 ****v logic currents (t min to t max ) i ih C10 +10 **** m a i il 0 60 100 *** 0 100 200 C m a v th pin voltage 1.4 v coding binary, offset binary current output ranges 0 to 10.24, 5.12 ma voltage output ranges 0 to 1.024, 0.512 v output compliance C2 +1.2 * * * * v output resistance exclusive of r l 160 200 240 * * * * * * w inclusive of r l 99 100 101 * * * * * * w reference amplifier input bias current 1.5 * * m a slew rate 3 * * % of fs/ns large signal bandwidth 10 * * mhz small signal bandwidth 15 * * mhz undervoltage recovery time v ref /v nom to 0% 35 * * ns
AD668j/a AD668k AD668s parameter min typ max min typ max min typ max units ac characteristics analog settling time (10% to 120% step) to 1% 60 * * ns to 1% of fsr to 0.1% 90 * * ns to 0.1% of fsr to 0.025% 120 * * ns to 0.025% of fsr digital settling time current to 1% 30 * * ns to 1% of fsr to 0.025% 90 * * ns to 0.025% of fsr voltage (100 w internal r l ) 3 to 1% 50 * * ns to 1% of fsr to 0.1% 75 * * ns to 0.1% of fsr to 0.025% 110 * * ns to 0.025% of fsr glitch impulse 4 350 * * pv-sec peak amplitude 20 * * % of fsr total harmonic distortion 5 C75 * * db multiplying feedthrough error 6 C62 * * db full-scale transition 2 10% to 90% rise time 11 * * ns 90% to 10% fall time 11 * * ns power requirements +10.8 v to +16.5 v 27 32 **ma C10.8 v to C16.5 v 7 9 * * Cma power dissipation 510 615 * * mw psrr 7 0.05 * * % of fsr/v temperature range rated specification 2 (j, k, s) 0 +70 * * C55 +125 c rated specification (a) C40 +85 c storage C65 +150 * * * * c notes *same as AD668j/a. 1 measured in i out mode. specified at nominal 5 v full-scale reference. 2 measured in v out mode, unless otherwise specified. specified at nominal 5 v full-scale reference. 3 total resistance. refer to figure 4. 4 at the major carry, driven by hcmos logic. 5 v out = 1 v p-p, v in = 10% to 110%, 100 khz. digital input all 1s. 6 v in = 200 mv p-p, 1 mhz sine wave. digital input all 0s. see figure 20. 7 measured at 15 v 10% and 12 v 10%. specifications shown in boldface are tested on all producfion units at final elec- trical test. specifications subject to change without notice. absolute maximum ratings* v cc to refcom . . . . . . . . . . . . . . . . . . . . . . . . 0 v to +18 v v ee to refcom . . . . . . . . . . . . . . . . . . . . . . . . . .0 v to C18 v refcom to lcom . . . . . . . . . . . . . . . . . . +100 mv to C10 v acom to lcom . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mv thcom to lcom . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mv refcom to refin (1, 2) . . . . . . . . . . . . . . . . . . . . . . . . 18 v i bpo to lcom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 v i out to lcom . . . . . . . . . . . . . . . . . . . . . . . . . . . . C5 v to v th digital inputs to thcom . . . . . . . . . . . . . C500 mv to +7.0 v refin1 to refin2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 v v th to thcom . . . . . . . . . . . . . . . . . . . . . . C0.7 v to +1.4 v logic threshold control input current . . . . . . . . . . . . . 5 ma power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 mw storage temperature range q (cerdip) package . . . . . . . . . . . . . . . . . . C65 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175 c thermal resistance q ja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +75 c/w q jc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 c/w *stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. AD668 rev. a C3C
AD668 rev. a C4C ordering guide linearity voltage temperature error max gain t.c. package model 1 range @ 25 c max ppm/ c option 2 AD668jq 0 c to +70 c 1/2 30 q-24 AD668kq 0 c to +70 c 1/4 15 q-24 AD668aq C40 c to +85 c 1/2 30 q-24 AD668sq C55 c to +125 c 1/2 40 q-24 notes 1 for details on grade and package offerings screened in accordance with mil-std-883, refer to the analog devices military products databook or current AD668/883b data sheet. 2 q = cerdip. definitions linearity error (also called integral nonlinear- ity or inl): analog devices defines linearity error as the maximum deviation of the actual analog output from the ideal output (a straight line drawn from 0 to fs) for any bit combina- tion expressed in multiples of 1 lsb. the AD668 is laser trimmed to 1/4 lsb (0.006% of fs) maximum linearity error at +25 c for the k version and 1/2 lsb for the j and s versions. differential linearity error (also called differ- ential nonlinearity or dnl): dnl is the measure of the variation in the analog output, normalized to fun scale, asso- ciated with a 1 lsb change in digital input code. monotonicity: a dac is said to be monotonic if the out- put either increases or remains constant as the digital input in- creases. monotonic behavior requires that the differential linearity error not exceed 1 lsb in the negative direction. unipolar offset error (dac offset): the dac offset is the portion of the dac output that is independent of the digital input. the unipolar dac offset error is measured as the deviation of the analog output from the ideal (0 v or 0 ma) when the analog input is set to 100% and the digital inputs are set to all 0s. bipolar offset error: the deviation of the analog out- put from the ideal (negative half-scale) when the dac is con- nected in the bipolar mode (pin 16 connected to pin 20), the analog input is set to 100%, and the digital inputs are set to all 0s is called the bipolar offset error. bipolar zero error: the deviation of the analog output from the ideal (0 v or 0 ma) for bipolar mode when only the msb is on (100 . . . 00) is called bipolar zero error. compliance voltage: the allowable voltage excursion at the output node of a dac which will not degrade the accu- racy of the dac output. settling time (digital channel): the time re- quired for the output to reach and remain within a specified error band about its final value, measured from the digital input transition. settling time (analog channel): the time re- quired for the output to reach and remain within a specified er- ror band about its final value, measured from the analog inputs crossing of its 50% value. gain error: the difference between the ideal and actual output span of fs C 1 lsb, expressed either in % of fs or lsb, when all bits are on is called the gain error. pin configuration
AD668 rev. a C5C analog offset error: the analog offset is defined as the offset of the analog amplifier channel, referred to the analog input. ideally, this would be measured with the analog input at 0 v and the digital input at full scale. since a 0 v analog input voltage constitutes an undervoltage condition, this specification is determined through linear extrapolation, as indicated in figure 1. figure 1. derivation of analog offset voltage glitch impulse: asymmetrical switching times in a dac may give rise to undesired output transients which are quanti- fied by their glitch impulse. it is specified as the net area of the glitch in pv-sec. figure 2. AD668 major carry glitch functional description the AD668 is designed to combine excellent performance with maximum flexibility. the functional block diagram and the simple transfer functions provided below will provide the user with a basic grasp of the AD668s operation. examples of typi- cal circuit configurations are provided in the section apply- ing the AD668. subsequent sections contain more detailed information useful in optimizing dac performance in high speed, high resolution applications. dac transfer function the AD668 may be used either in a current output mode (dac output connected to a virtual ground) or a voltage output mode (dac output connected to a resistive load). in current output mode: unipolar mode i out = v in v nom dac code 4096 10.24 ma bipolar mode i out = v in v nom dac code 4096 10.24 ma v in v nom 5.12 ma in voltage output mode: v out = i out r load (for both unipolar and bipolar modes) where: v in C the analog input voltage. v nom C the nominal full scale of the reference voltage: 1 v, 1.25 v, or 5 v, determined by the wiring configuration of pins 21 and 22. (see applying the AD668.) dac code C the numerical representation of the dacs digital inputs; a number between 0 and 4095. r load C the resistance of the dac output node; the maximum this can be is 200 w (the internal dac ladder resistance). the on-board load resistor (pin 19) has been trimmed so that its parallel combination with the dac ladder resistance is 100 w ( 1%) bipolar mode C produces a bipolar analog output from the digital input by offsetting the normal output current with a precision current source. this offset is achieved by connecting pin 16 to the dac output. in the unipolar mode, pin 16 should be grounded. if the dc errors are included, the transfer function becomes somewhat more complex: i out = v in v nom + offset analog ? ? ? ? dac code 4096 (1 + e ) 10.24 ma + offset digital v in v nom 10.24 ma v in v nom + offset analog ? ? ? ? (5.12 ma + [ offset bipolar 10.24 ma ]) (last term is for use in bipolar mode; v out is still just i out r load ) where: offset analog = the analog offset error. offset digital = is the unipolar digital offset error. offset bipolar = is the bipolar offset error. e = the gain error, expressed fractionally. operating limits:
AD668 rev. a C6C 0.1 < v in v nom < 1. 2 0 < v in /v nom < 0.1 constitutes an undervoltage condition and is subject to the specified recovery time. 1.2 < v in /v nom constitutes an overvoltage condition. this can saturate the dac transistors, resulting in decreased response time and can, over extended time, damage the part through ex- cessive power dissipation. figure 3 indicates the specified re- gions of operation in both the unipolar and bipolar cases. the small signal 3 db bandwidth of the v in channel is 15 mhz. the large signal 3 db bandwidth is approximately 10 mhz. v out is limited by the specified output compliance: C2 v to +1.2 v. figure 3. quadrant plots of the AD668 circuit description of the AD668 successful design of high speed, high resolution systems de- mands a designers solid working knowledge of the components being used. the AD668 has been carefully configured to pro- vide maximum functionality in a variety of applications. while it is beyond the scope of this data sheet to exhaustively cover each potential application topology, the detailed information that follows is intended to provide the designer with a sufficiently thorough understanding of the parts inner workings to allow selection of the circuit topology to best suit the application. current output vs. voltage-output as indicated in the functional description, the AD668 output may be taken as either a voltage or a current, depending on external circuit connections. in the current output mode, the dac output (pin 20) is tied to a summing junction, and the current flowing from the dac into this summing junc- tion is sensed. in this mode, the dac output scale is insensitive to whether the load resistor, r load , is shorted (pin 19 con- nected to pin 20), or grounded (pin 19 connected to pin 18). however, the connection of this resistor does affect the output impedance of the dac and may have a significant impact on the noise gain and stability of the external circuitry. grounding r load will reduce the output impedance, thereby increasing the noise gain and also enhancing the stability of a circuit using a non-unity-gain-stable op amp (see figure 10). in the voltage output mode, the dacs output current flows through its own internal impedance (perhaps in parallel with an external impedance) to generate a voltage. in this case, the dac output scale is directly dependent on the load impedance. the temperature coefficient of the AD668s transfer function will be lowest when used in the voltage output mode. output voltage compliance the AD668 has an output compliance range of C2.0 v to +1.2 v (with respect to the lcom pin). the current steering output stages will be unaffected by changes in the output termi- nal voltage over this range. however, as shown in figure 4, there is an equivalent output impedance of 200 w in parallel with 15 pf at the output terminal, producing an equivalent er- ror current if the voltage deviates from the ladder common. this is a linear effect which does not change with input code. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in non- linear performance. the positive compliance limit is not af- fected by the positive power supply, but is a function of the output current and the logic threshold voltage at v th , pin 13. figure 4. equivalent output circuit analog input considerations the reference input buffer can be viewed as a resistive divider connected to one terminal of an op amp, as shown in figure 5. a unit dac current source drives a resistor to produce a voltage that is fed back to the opposite terminal of the op amp. resistor r feedback is laser-trimmed to ensure that a 1 v input to node a of the op amp will produce a 10.24 ma dac output. refin1 and refin2 may be configured in any way the user chooses to pro- vide a nominal input full scale of 1 v at node a. r1 and r2 are sized and trimmed to provide both a 5:1 voltage divider and a parallel impedance that matches the impedance at node b, thereby reducing the amplifier offset voltage due to bias current. the resistive divider is trimmed with an external 50 w resistor in series with the 4k leg (r2). this provides a gain trim range of 1% using a 100 w trim potentiometer (figure 7). if trimming is not desired, a 50 w resistor may be used in place of the potentiom- eter to produce the specified gain accuracy, or the resistor may be omitted altogether to produce a nominal gain error of +1%. figure 5. equivalent analog input circuitry
AD668 rev. a C7C the variations in dac settling and rise times can be attributed to differences in rise time and current driving capabilities of the various families. differences in the glitch impulse are predomi- nantly dependent upon the variation in data skew. variations in these specs occur not only between logic families, but also be- tween different gates and latches within the same family. when selecting a gate to drive the AD668 logic input, pay particular attention to the propagation delay time specs: t plh and t phl . selecting the smallest delays possible will help to minimize the settling time, while selection of gates where t plh and t phl are closely matched to one another will minimize the glitch impulse resulting from data skew. of the common latches, the 74374 octal flip-flop provides the best performance in this area for many of the logic families mentioned above. pin by pin current accounting the internal wiring and pinout of the AD668 are dictated in large part by current management constraints. when using low impedance, high current, high accuracy parts such as the AD668, great care must be taken in the routing of not only sig- nal lines, but ground and supply lines as well. the following ac- counting provides a detailed description of the magnitudes and signal dependencies of the currents associated with each of the parts pins. these descriptions are consistent with the functional block diagram as well as the equivalent circuits provided in fig- ures 4, 5, and 6. v cc C the current into this pin is drawn predominantly through the dac current sources and generally runs about 2.2 times the dacs nominal full scale. by design, this current is independent of the digital input code but is linearly dependent on analog in- put variations. refcom C this node provides the reference ground for the reference amplifiers current feedback loop (as illustrated in fig- ure 5) as well as providing the negative supply voltage for most of the reference amplifier. the current consists of 1.2 ma of analog input dependent current and another 3 ma of input in- dependent current. analog input voltages should always be pro- duced with respect to this voltage. refin1 C has a 1k series resistance to the reference amplifier input and a 5k series resistance to refin2. refin1 may be used in conjunction with refin2 to provide a 5:1 voltage di- vider, or the two may be driven in parallel to provide a high impedance input node (see figure 5). refin2 C the 4k side of the input resistive divider. note also that the combined impedance of these two resistors matches the effective impedance at the other input of the reference amplifier, thereby minimizing the offset due to bias currents. circuits which alter this effective impedance may suffer increased analog offset and drift performance degradation as a result of the mis- match in these impedances. i out C the output current. in the current output mode with this node tied to a virtual ground, a 10.24 ma nominal full scale output current will flow from this pin. in the voltage output mode, with r l grounded, half of the output current will flow out of r l and the other half will flow out of lcom. external resistive loading will cause current to be divided between lcom, r l , and i out as figure 4 suggests. digital input considerations the AD668 uses a standard positive true straight binary code for unipolar outputs (all 1s full-scale output), and an offset bi- nary code for bipolar output ranges. in the bipolar mode, with all 0s on the inputs, the output will go to negative full scale; with 111 . . . 11, the output will go to positive full scale less 1 lsb; and with 100 . . . 00 (only the msb on), the output will go to zero. the threshold of the digital inputs is set at 1.4 v and does not vary with supply voltage. this reference is provided by a band- gap generator, which requires approximately 3 ma of bias current achieved by tying r th to any +v logic supply where: r th = + v logic 1.4 v 3 ma ? ? ? ? (see figure 6). the digital bit inputs operate with small input currents to easily interface to unbuffered cmos logic. the digi- tal input signals to the dac should be isolated from the analog input and output as much as possible. to minimize undershoot, ringing, and digital feedthrough noise, the interconnect distance to the dac inputs should be kept as short as possible. termina- tion resistors may improve performance if the digital lines be- come too long. the digital inputs should be free from large glitches and ringing and have 10% to 90% rise and fall times on the order of 5 ns. figure 6. equivalent digital input to realize the AD668s specified ac performance, it is recom- mended that high speed logic families such as schottky ttl, high speed cmos, or the new lines of high speed ttl be used exclusively. table i shows how dac performance, particularly glitch, can vary depending on the driving logic used. as this table indicates, sttl, hcmos, and fast* represent the most viable families for driving the AD668. table i. dac performance vs. drive logic 10%-90% 2 settling time 2, 3 maximum logic dac rise 1 lsb glitch 4 glitch family 1 time 1% 0.1% (0.025%) impulse excursion ttl 10.5 ns 47 ns 77 ns 100 ns 2.5 nv-s 280 mv lsttl 11.25 ns 35 ns 60 ns 120 ns 1.2 nv-s 270 mv sttl 11 ns 50 ns 75 ns 110 ns 500 pv-s 200 mv hcmos 12 ns 53 ns 78 ns 100 ns 350 pv-s 200 mv fast* 11.5 ns 49 ns 73 ns 100 ns 2 nv-s 250 mv notes 1 all values typical, taken in test fixture diagrammed in figure 23. 2 measurements are made for a 1 v full-scale step into 100 w dac load resistance. 3 settling time is measured from the time the digital input crosses the threshold voltage (1.4 v) to when the output is within the spe cified range of its final value. 4 the worst case glitch impulse, measured on the major carry. dac full scale is1 v. *fast is a registered trademark of national semiconductor corporation.
AD668 rev. a C8C r l C a 200 w resistor with one end internally wired to the out- put pin. if a 200 w 20% dac output impedance is desired, r l should be shorted to i out . grounding r l will provide a dac output impedance of 100 w 1%. as noted above, in voltage output configurations, a large portion of the dac output cur- rent will flow through this pin. acom - as indicated in figure 4, the current flowing out of this pin is effectively the complement of i out , varying with both analog and digital inputs. using this current as a signal output is not generally advised, since it is untrimmed and its positive out- put compliance is limited to the logic low voltage. lcom - the current in this node has been carefully configured to be independent of digital code when the output is into a vir- tual ground, thereby minimizing any detrimental effects of lad- der ground resistance on linearity. however, the current in this node is proportional to the analog input voltage and the ground drop here is responsible for the dc analog feedthrough. the nominal value of this current is approximately equal to the dac full scale. ibpo - the bipolar offset current flows into this node, with volt- age compliance to v ee + 3v. this is a high impedance current source, and should be grounded if the offset current is not used. v ee - this voltage may be set anywhere from C10.8 v to C16.5 v. the current in this node consists of 1.2 times the bipo- lar offset current plus 500 m a of bias current for the reference amplifiers front end. the negative supply current is indepen- dent of digital input but is linearly dependent on analog input. thcom - is the ground point for the bandgap diode that gen- erates the threshold voltage. the current coming out of this node is the same as that flowing into v th plus a code dependent number of base currents (see figure 6). it is possible to intro- duce an offset between thcom and the system common, thereby offsetting the effective logic threshold and positive out- put compliance voltage. v th - as indicated earlier, if given sufficient positive bias cur- rent, this voltage will be 1.4 v above thcom. the necessary bias current can readily be provided by a suitable resistor to any positive supply. as figure 6 suggests, this node is directly coupled to the dac output through several base to collector capacitances and hence, should be carefully decoupled to the analog ground. digital inputs - when a bit is in the high state, the input current is the leakage current of a reverse biased diode. when the bit is driven low, it must sink a base current to ground, and this base current will be proportional to the analog input. note that the input current for bit 2 will be twice that for bits 3-12, and bit 1s current will be 4 times bit 3s, but all the currents will be below the value specified. applying the AD668 the following are some typical circuit configurations for the AD668. as table ii indicates, these represent only a sample of the possible implementations. 5 v refin, 1 v unipolar, unbuffered voltage output figure 7 shows a typical topology for generating an unbuffered voltage output. r l (pin 19) is grounded, producing a 100 w dac output resistance that generates a 1.024 v output when the dac current is at its full scale of 10.24 ma. the presence of low impedance loads will effect the output voltage swing di- rectly: an external load of 300 w will yield a total output resis- tance of 75 w , and a full scale output of 0.768 v. an external 100 w will reduce the total output resistance to 50 w and the full-scale voltage swing will drop to 0.512 v. since the bipolar offset current is not used in this configuration, pin 16 is con- nected to the analog ground plane. the input divider has been connected to produce a 5 v full scale reference input by shorting refin1 to the analog ground plane and using refin2 as the reference input. with a 5 v nominal full scale, the 10% to 120% reference input range falls between 0.5 v and 6 v. the effective input resistance in this mode is 5 k w ( 20%). the ratio of the input divider has been intentionally skewed by 50 w to provide an optional external fine trim for gain adjust. a trim range of 1% is provided by the 100 w trimming potentiometer shown in figure 7. if trimming is not desired, a 50 w resistor may be used in place of the poten- tiometer to produce the specified gain accuracy, or, if a +1% nominal gain error is tolerable, the resistor may be omitted altogether. figure 7. 5 v refin/1 v unbuffered unipolar output 1.25 v refin, 1 v bipolar, unbuffered voltage output figure 8 demonstrates another unbuffered voltage output topol- ogy, this time implementing a bipolar output and a 1.25 v refer- ence input. the bipolar output is accomplished simply by tying pin 16 to the output (pin 20). note that in this mode, when the digital inputs are all zeros and the analog input is at 1.25 v, C512 mv will be produced at the dac output. bipolar zero (0 v out ) will be produced when the msb is on with all other bits off (100 . . . 00), and the full-scale voltage minus 1 lsb (511.75 mv) will be generated when all bits are on. the input range of 1.25 v is generated by grounding refin2 (through an optional gain trim potentiometer or gain adjust 50 w resistor) and using refin1 as the reference input. the input resistance in this mode is also 5k.
AD668 rev. a C9C figure 8. 1.25 v refin/ 500 mv unbuffered bipolar output 5 v refin, 2 v bipolar, unbuffered voltage output figure 9 demonstrates how a larger unbuffered voltage output swing can be realized. r load (pin 19) is tied to the dac output (pin 20) to produce an output resistance of roughly 200 w . figure 9. 5 v refin/ 1 v unbuffered bipolar output it should be noted that this impedance is not trimmed, and may vary by as much as 20%, but this can be compensated by adjust- ing the reference voltage. it is also important to note that limita- tions in the dac output compliance would prohibit use of a 2 v unipolar output voltage swing. 1 v refin, C10 v unipolar, buffered voltage output figure 10 shows the implementation of the 1 v full scale for the reference input by tying refin1 and refin2 together and driving them both with the input voltage. this generates a high input impedance, and some care should be taken to insure that the driving impedance at this node is finite at all times to avoid saturating the reference amplifier. this is typically accomplished by a using a low impedance voltage source to drive the refer- ence, but if the topology calls for this source to be switched out, a high impedance (10 k w ) termination resistor should be used on the refin node. figure 10. 1 v refin/C10 v unipolar buffered output for full-scale output ranges greater than 2 v, some type of ex- ternal buffer amplifier is needed. the ad840 fills this require- ment perfectly, settling to within 0.025% from a 10 v full-scale step in less than 100 ns. as shown in figure 10, the amplifier establishes a summing node at ground for the dac output. the output voltage is determined by the amplifiers feedback resistor (10.24 v for a 1k resistor). note that since the dac generates a positive current to ground, the voltage at the amplifier output will be negative. a series resistor between the noninverting am- plifier input and ground minimizes the offset effects of op amp input bias currents. the optimal dac output impedance in buffered output appli- cations depends on the buffer amplifier being used. the ad840 is stable at a gain of 10, so a lower dac output impedance (higher noise gain) is desired for stability reasons, and r load should be grounded. the 100 w dac output impedance pro- duces a noise gain of 11 with the 1k feedback resistor. if the gain-of-two stable ad842 is used as a buffer, a 200 w dac out- put impedance will produce a stable configuration with lower noise gain to the output; hence, r load should be connected to the dac output. as noted earlier, these four examples are part of an array of possible configurations available. table ii provides a quick reference chart for the more straightforward applications, but many other input and output signals are possible with some modifications. the next three circuits provide examples of different analog in- put drives, including a fixed dc reference, a capacitively coupled ac reference, and a dac driving the reference channel. note that the entire spectrum of input and output range configura- tions are available regardless of the type of reference drive being used. dc reference: the ad586 driving the AD668 figure 11 illustrates one of the more obvious analog input sources: a fixed reference. the ad586 produces a temperature stable 5 v analog output to drive the AD668 in the 5 v input
AD668 rev. a C10C figure 11. ad586 driving the AD668 mode (pin 22 grounded, input into pin 21). fine adjustment of the gain is provided by both the ad586 external trim resistor and the 100 w potentiometer in series with the reference input. the resistive divider at the reference input will draw approxi- mately 1 ma from the ad586, leaving plenty of driving current for other loads in the system. ac hookup: 1.25 v ac full scale, 2.5 v dc full scale the circuit shown in figure 12 allows separate setting of dc ref- erence bias point on a 2.5 v scale and capacitively coupled ac signal on a 1.25 v scale. the basic reference input is configured in the 1.25 v mode (pin 21 grounded, pin 22 used as the refer- ence input.) the 2.5 v dc range is achieved by using an external table ii. AD668 topology variations output levels nominal analog input 0 v to 1 v C500 mv to +500 mv 0 v to C10 v +5 v to C5 v C1 v to +1 v unipolar bipolar unipolar bipolar bipolar 1 v unbuffered v out unbuffered v out buffered v out buffered v out unbuffered v out a in = pins 21 + 22 a in = pins 21 + 22 a in = pins 21 + 22 a in = pins 21 + 22 a in = pins 21 + 22 external amplifier external amplifier r l (pin 19) tied (see figure 10) to i out (pin 20) unipolar bipolar unipolar bipolar bipolar unbuffered v out unbuffered v out buffered v out buffered v out unbuffered v out 1.25 v a in = pin 22 a in = pin 22 a in = pin 22 a in = pin 22 a in = pin 22 pin 21 grounded pin 21 grounded pin 21 grounded pin 21 grounded pin 21 grounded (see figure 8) external amplifier external amplifier r l (pin 19) tied to i out (pin 20) unipolar bipolar unipolar bipolar bipolar unbuffered v out unbuffered v out buffered v out buffered v out unbuffered v out 5 v a in = pin 21 a in = pin 21 a in = pin 21 a in = pin 21 a in = pin 21 pin 22 grounded pin 22 grounded pin 22 grounded pin 22 grounded pin 22 grounded (see figure 7) external amplifier external amplifier r l (pin 19) tied to i out (pin 20) (see figure 9) 5k series resistor in the dc path. note that because of the rela- tively wide tolerance ( 20%) in the absolute value of the AD668s internal input divider resistors, substantial gain range adjustment should be provided in the external series resistance. figure 12. ac hookup dac drive: the ad568 driving the AD668 the circuit shown in figure 13 produces an analog output pro- portional to the product of two digital inputs. the ad568 has an on-board fixed reference and generates a full-scale output voltage of 1.024 v (just as the AD668 does in its unbuffered voltage output mode). this output voltage can be used to di- rectly drive the AD668 in the 1 v reference input mode. note that in this case, the lower 410 codes of the ad568 are out-of- bounds; they produce an undervoltage condition at the AD668
AD668 rev. a C11C reference input. while the two dacs are similar in many ways, the optimal decoupling schemes differ between the two parts and care should be used to insure that each is implemented appropriately. figure 13. ad568 driving the AD668 construction guidelines high frequency printed circuit board suggestions in systems seeking to simultaneously achieve high speed and high accuracy, the implementation and construction of the cir- cuit is often as important as the circuits design. proper rf techniques must be used in device selection, placement and routing, and supply bypassing and grounding. in many areas, the performance of the AD668 may exceed the measurement ca- pabilities of common lab instruments, making performance evaluation particularly difficult. the AD668 has been config- ured to be relatively easy to use in spite of these problems, and realization of the performance indicated in this datasheet should not be difficult if proper care is taken. figure 14 provides an il- lustration of the printed circuit board layout used for much of the AD668s characterization. the board represents an imple- mentation of the circuit shown in figure 23, with the ad586 used to drive the reference channel (as in figure 11). component side foil side figure 14. pc board layout the use of ground and power planes if properly implemented, ground planes can perform a myriad of functions on high speed circuit boards: bypassing, shielding, current transport, etc. in mixed signal design, the analog and digital portions of the board should be distinct from one an- other, with the analog ground plane confined to areas covering analog signal traces and the digital ground plane confined to areas covering digital interconnect. the two ground planes should be connected by paths 1/4 inch to 1/2 inch wide on both sides of the dac, as shown in figure 14. care should be taken to insure that the ground plane is uninterrupted over crucial sig- nal paths. on the digital side, this includes the digital input lines running to the dac, as well as any clock signals. on the analog side, this includes the analog input signal, the dac output sig- nal, and the supply feeders. the use of wide runs or planes in the routing of the power supplies is also recommended. this serves the dual function of providing a low series impedance power supply to the part as well as providing some free ca- pacitive decoupling to the appropriate ground plane. using the right bypass capacitors the capacitors used to bypass the power supplies are probably the most important external components in any high speed de- sign. both selection and placement of these capacitors can be critical and, to a large extent, dependent upon the specifics of the system configuration. the dominant consideration in the selection of bypass capacitors for the AD668 is minimization of series resistance and inductance. many capacitors will begin to look inductive at 20 mhz and above. ceramic and film type capacitors generally feature lower series inductance than tanta- lum or electrolytic types. a few general rules are of universal use when approaching the problem of bypassing. bypass capacitors should be installed on the printed circuit board with the shortest possible leads consistent with reliable construction. this helps to minimize series inductance in the leads. chip capacitors are optimal in this respect. some series inductance between the dac supply pins and the power supply plane may help to filter-out high frequency power supply noise. this inductance can be generated using a small ferrite bead.
AD668 rev. a C12C high speed interconnect and routing it is essential that care be taken in the signal and power ground circuits to avoid inducing extraneous voltage drops in the signal ground paths. it is suggested that all connections be short, di- rect, and as physically close to the package as possible, thereby minimizing the sharing of conduction paths between different currents. when runs exceed an inch or so in length, some type of termination resistor may be required. the necessity and value of this resistor will be dependent upon the logic family used. for maximum ac performance, the dac should be mounted di- rectly to the circuit board; sockets should be avoided as they in- troduce unwanted capacitive coupling between adjacent pins of the device. for purposes of testing and characterization, low profile sockets are preferable to zero insertion force types. typical performance characteristics the following plots indicate the typical performance of the AD668 in properly configured circuits. wherever possible, sug- gestions are provided to assist the user in achieving the indicated performance levels. dc performance power consumption vs. v ref /v nom as suggested in previous sections, most portions of AD668s current budget are proportional to the analog input signal. as a result, operating the part at a reduced reference voltage offers substantial power savings. this may be particularly attractive in applications featuring a buffered output voltage, since the size of the feedback resistor may be increased to compensate for the re- duced dac current. for example, the dac could be config- ured in the 5 v input mode, but driven with a 2.5 v reference, producing a 5.12 ma full scale output. reducing the output level has performance ramifications in several areas, as demon- strated later in this section, but the circuit designer is free to trade power dissipation against performance to optimize the AD668 for his application. figure 15. power consumption vs. reference level linearity vs. v ref /v nom at reduced current levels, the linearity of the pnp dac used in the AD668 becomes more sensitive to the mismatch in transis- tor v be s. as figure 16 indicates, this effect starts to increase fairly dramatically for reference levels less than 25% of nominal. increasing the current level above 100% does not appreciably improve the linearity performance since the dac has been trimmed to perform optimally at the 100% reference level. figure 16. linearity vs. reference level ac performance for the purposes of characterizing the frequency domain perfor- mance of the AD668, all bits are turned on and the dac is es- sentially treated as a voltage amplifier/attenuator. the tests used to generate these performance curves were done using the cir- cuit shown in figure 12. ac characterization in the megahertz region is not trivial, and special consideration is required to produce meaningful results. probe ground straps are inappropriate at these frequencies; some type of probe socket is required. signals should be routed either on a pc board over a ground plane or through a coaxial cable. proper termination impedances should be used through- out the fixturing. large signal frequency response figure 17 represents the gain and phase response of a signal swinging from 10% to 120% (peak to peak) of the nominal ref- erence input. the dac reference amplifier has an effective slew rate or 30 v/ m s at the dac output, so there will be slew-induced distortion for full scale swings at greater than 10 mhz. figure 17. large signal gain and phase response small signal 3 db bandwidth vs. v ref /v nom figure 18 demonstrates the small signal (20% of nominal refer- ence) bandwidth sensitivity to the analog inputs dc bias. the small signal 3 db bandwidth at 100% reference levels is greater than 15 mhz, but the bandwidth remains greater than 10 mhz over the entire nominal reference range. the differential gain and phase for a 200 mv, 3 mhz signal are 0.5% and 2 , respectively.
AD668 rev. a C13C figure 18. small signal bandwidth vs. dc reference level noise spectrum figure 19 shows the noise spectrum of the dac with all bits on. the noise floor of C78 db is just above the noise floor of the in- strument being used, in part due to the relatively small (1 v) output signal of the dac in voltage output mode. figure 19. noise spectrum analog feedthrough vs. frequency analog feedthrough is a measure of the effective signal at the dac output when all bits are off and a full-scale signal is placed at the analog input. at dc, the feedthrough is a result of analog input dependent ground drops, predominantly through the lad- der ground. good grounding practices will minimize this effect. at high frequencies, the signal may propagate to the output through a variety of capacitive paths. proper shielding and rout- ing should be implemented to eliminate external coupling be- tween the analog input and the dac output node. figure 20. analog feedthrough vs. frequency reference channel thd thd, or total harmonic distortion, is the ratio of the rootmean-square (rms) sum of the harmonics to the fundamen- tal and is expressed in dbs. figure 21 shows the typical thd of the AD668 reference channel for both large and small signals. figure 21. reference channel thd vs. frequency transient performance high accuracy settling time measurements of less than one hun- dred nanoseconds are extremely diliicult to make. the conven- tional analog amplifiers used in oscilloscope front ends, typically, cannot recover from the overdrive resulting from a full-scale step in sufficient time. sampling scopes can track much quicker rise times but often provide insufficient accuracy for 12-bit characterization. data precisions new 640 sampling scope provides a good combination of speed and resolution that provides just enough performance to measure the AD668s performance. digital settling time figure 22 illustrates the typical settling characteristic of the AD668 to a full-scale change in digital inputs with the analog input fixed at 100%. the digital driving circuity is shown in figure 23. this circuit allows the dac to be toggled between any two codes, and so provides an excellent means of character- izing both settling and glitch performance. figure 22. typical digital settling characteristics
AD668 rev. a C14C figure 23. settling time circuit digital settling time vs. v ref the reference amplifier loop has been compensated for optimal settling performance at v ref /v nom = 100%, but as figure 24 indicates, there is relatively little degradation in settling perfor- mance for a wide range of reference levels. consideration of figures 15, 16, and 24 support that a 1/2 power solution would see very little degradation in speed or accuracy performance. figure 24. digital settling time vs. reference level analog settling time one of the biggest challenges in measuring the settling time of a high accuracy amplifier is producing a clean waveform with which to drive the input. in this case, an ad568 was used to drive the analog channel in the 1 v input mode (see figure 13). as indicated by figure 25, the referred-to-output slew rate is 30 v/ m s for a 1 v output. this implies that a full-scale analog input sine waves of greater than 10 mhz frequency will suffer some slew-induced distortion. it should be noted that the slewing limitation is in the reference amplifier, not in the dac output, so a 10 v buffered output voltage would slew at 300 v/ m s, provided the output buffer is sufficiently fast. figure 25. typical analog settling characteristic undervoltage recovery time the ramifications of exceeding the specified lower limit of 10% on the reference channel depend on the extent and duration of the undervoltage condition. figure 26 illustrates that, after hold- ing the reference at 0% (refin = refcom) for 1 m s, the AD668 takes 35 ns to return to 10% of full scale once the refer- ence is returned to 100%. this is the worst case: recovery from a completely off condition. figure 26. undervoltage recovery glitch impulse the AD668s glitch at the major carry is illustrated in figure 2. the AD668 features a conventional dac architecture that has two basic glitch mechanisms: digital feedthrough and data skew. careful consideration of these mechanisms will help the glitch- conscious user minimize glitch in his application. digital feedthrough as with any converter product, a high speed digital-to-analog converter is forced to exist on the frontier between the noisy environment of high speed digital logic and the sensitive analog domain. the problems of this interfacing are particularly acute when demands of high speed (greater than 10 mhz switching times) and high precision (12 bits or more) are combined. no amount of design effort can perfectly isolate the analog portions of a dac from the spectral components of a digital input signal with a 2 ns rise time. inevitably, once this digital signal is brought onto the chip, some of its higher frequency components will find their way to the sensitive analog nodes, producing a digital feedthrough glitch. to minimize the exposure to this ef- fect, the AD668 has intentionally omitted the on-board latches that have been included in many slower dacs. this not only reduces the overall level of digital activity on chip, it also avoids
AD668 rev. a C15C bringing a latch clock pulse on board, whose opposite edge in- evitably produces a substantial glitch, even when the dac is not supposed to be changing codes. data skew the AD668, like many of its slower predecessors, essentially uses each digital input line to switch a separate, weighted cur- rent to either the output (i out ) or some other node (analog com). if the input bits are not changed simultaneously, or if the different dac bits switch at different speeds, then the dac output current will momentarily take on some incorrect value. this effect is particularly troublesome at the carry points, where the dac output is to change by only one lsb, but sev- eral of the larger current sources must be switched to realize this change. data skew can allow the dac output to move a sub- stantial amount towards full scale or zero (depending upon the direction of the skew) when only a small transition is desired. great care was taken in the design and layout of the AD668 to ensure that switching times of the dac switches are symmetri- cal and that the length of the input data lines are short and well matched. the glitch-sensitive user should be equally diligent about minimizing the data skew at the AD668s inputs, particu- larly for the 4 or 5 most significant bits. this can be achieved by using the proper logic family and gate to drive the dac, and keeping the interconnect lines between the log outputs and the dac inputs as short and as well matched as possible, particu- larly for the most significant bits. the top 6 bits should be driven from the same latch chip if latches are used. deglitching for precision waveform generation there are high speed shas available with specifications suffi- cient to deglitch the AD668, however most are hybrid in design at costs which can be prohibitive. a high performance, low cost alternative shown in figure 27 is a discrete sha utilizing a high speed monolithic op amp and high speed dmos fet switches. this sha circuit uses the inverting integrator architecture. the ad841 operational amplifier used (300 mhz gain bandwidth product) is fabricated on the same high speed process as the AD668. the time constant formed by the 100 w resistor and the 100 pf capacitor determines the acquisition time and also band limits the output signal to eliminate slew induced distortion. a discrete drive circuit is used to achieve the best performance from the sd5000 quad dmos switch. this switch driving cell is composed of mps571 rf npn transistors and an mc10124 ttl to ecl translator. using this technique provides both high speed and highly symmetrical drive signals for the sd5000 switches. the switches are arranged in a single-throw double- pole (spdt) configuration. the 360 pf flyback capacitor is switched to the op amp summing junction during the hold mode to keep switching transients from feeding to the output. this capacitor is grounded during sample mode to minimize its effect on acquisition time. circuit layout for a high speed deglitcher is almost as critical as the design itself. figure 28 shows the recommended layout of the deglitching cell for a double-sided printed circuit board. the layout is very compact with care taken that all critical signal paths are short. performance of the AD668 in waveform generation applications is greatly improved with the use of this deglitching method. peak harmonics and spurious free dynamic range are typically main- tained at -70 db to -75 db with update rates up to 10 mhz. 4 5 10 6 5 16 8 9 2 4 ad841 5v 5v + mc 10124 15v r11 20k to pin 2 sd5000 c1 0.039 m f r12 1.6k s/ h 5v 5v 15v r6 249 r7 169 r8 510 r10 249 r9 169 r5 360 r4 360 mps 571 (2) d1 in4735 input r1 100 r2 100 13 12 14 16 11 9 100pf c filt 6 3 8 5 4 1 360pf c hold r3 100 output 15v + figure 27. high performance, low cost deglitching circuit
AD668 rev. a C16C c1451C10C9/90 printed in u.s.a. outline dimensions dimensions shown in inches and (mm). 24-pin cerdip (suffix q) figure 28a. pcb layout of foil side figure 28b. pcb layout of component side

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